OBJECTIVE:
Seeking a full-time industry position in low power circuit-hardware-architecture design, logic design and verification, static timing analysis, reconfigurable computing and FPGA prototyping.
INDUSTRY WORK EXPERIENCE:
• Component Design Engineering Intern at Intel Corporation, Folsom CA (Current Position)
Working as a logic designer on a Canoe Lake Processor Test Chip mainly targeted for client CPU; specifically developing 16 GHz I/O standard to be used on the receiver side. Responsibilities mainly include
(a) Design of a digital offset calibration block which interfaces with a flash ADC (b) Design of logic equalizer block needed for communicating with graphics (c) Synthesis of logic blocks and optimization of area and power (d) Power consumption analysis using Presto Power Analyzer. (e) Full system digital simulation by interfacing with ADC Verilog models (f) Mixed signal simulation of real full system receiver. Expertise developed includes (a) Random Logic Synthesis (b) Timing Analysis (c) RTL coding and (d) Logic design and verification.
EDUCATIONAL BACKGROUND:
• Case Western Reserve University, Cleveland, OH, USA
- MS in Computer Engineering (May 2012), GPA – 3.8/4.0
• Indian Institute of Technology, Kharagpur, WB, India
- Research Consultant (June 2008 – May 2009).
• Jadavpur University, Kolkata, WB, India
- B.E. (with Hons.) in Electrical Engineering (May, 2008), GPA – 8.1/10.0
GRADUATE ACADEMIC WORK EXPERIENCE:
• Graduate Research Assistant (Summer 2011 – May 2012)
• Graduate Teaching Assistant (Fall 2009 – Digital Logic and Computer Organization, Spring 2010 - Digital Logic and Computer Organization, Fall 2010- Nanometer VLSI Design, Digital Logic Laboratory, Spring 2011-Computer Systems Architecture).
RESEARCH EXPERIENCE:
• Energy-Efficient Application Mapping in FPGA
o Low power implementation of logic based mapping, DSP block based mapping and memory-logic based heterogeneous mapping for variety of DSP/ multimedia and security applications
o Development of effective energy-accuracy tradeoff methodology for variety of DSP applications at run-time
• FPGA Based Prototyping Vehicle For a 2D Memory-Array Based Hardware Accelerator
o Completely validated framework for a memory based hardware accelerator containing multiple computing elements using embedded RAM for storage, instruction and compute logic (LUT).
• Back-End Development of a Custom Reconfigurable Hardware Accelerator
o SPICE modeling for standard logic cell like address decoding and selection logic of varying implementations and sizes, FPGA switch box and routing mux, 6T SRAM cell, etc.
• Front-End Development of a Custom Reconfigurable Hardware Accelerator
o Decomposition routines in C for various arithmetic and logic operations like multiplication, multi-input additions, logical operations etc.
• Tool development in MATLAB for modeling DNA translocation through a solid state nanopore and the impact on sensitivity for gold-coating on the DNA molecules
• Behavioral modeling of a MEMS based electron tunneling accelerometer for micro-g resolution acceleration sensing (Undergraduate Final Year Project)
MAJOR GRADUATE COURSES TAKEN:
1.Computer Systems Architecture 7. Statistical Signal Processing
2.MOS Integrated Circuit Design 8. Data Mining and Pattern recognition
3.VLSI Systems 9. Digital Signal Processing
4.Embedded Systems Design 10. Introduction to Nanotechnology
5.VLSI Digital Signal Processing 11. Microelectronic Analysis and Design
6.Nanometer VLSI Design 12. Micro-fabricated Silicon Electromechanical Systems
TECHNICAL SKILLS:
IC Design Software: P-Spice, LT-Spice
FPGA Design Software: Quartus, NIOS IDE, Altera Design Space Explorer, Xilinx ISE
Engineering Softwar...
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