Neo
EDUCATION
• SUNY-Stony Brook University GPA 3.72
M.S., Electrical and Electronic Engineering, ECE Department Aug 2012-Dec 2013
• Nanjing University of Posts and Telecommunications (NUPT) GPA 3.22
B.E., Electrical Engineering and Automation, School of Automations Oct 2003-July 2007
RELEVANT COURSE
Computer Archetecture, Advanced VLSI Systems Design, Solid-State Electronics, Integrated Electronic Devices and Circuits, Advanced Design of Low Noise& Low Power circuit, Hardware-Software Co-Design of Embedded Systems.
SKILLS AND EXPERTISE
VLSI, Cadence Virtuoso, Orcad, System Verilog, VHDL, Pspice, Modelsim, Matlab, Assembly, C, C++.
RELEVANT EXPERIENCE
•Brookhaven National Laboratory Summer intern Jun 2013-Sep 2013
-Transferred and verified ASIC front end channel circuit design within Cadence Orcad.
-Assisted the project of X-ray radiation detector, designed PCB board of the external circuit for ASIC.
•Guangzhou GISE Gases Co.,Ltd(Now Guangzhou Linde Gise Gases Co.,Ltd)
Electrical Engineer July 2007-Mar 2009
-Provided electronic devices installation and consultation service.
-Secured Product quality and electrical operational safety, development and debugging for on-site projects.
-Improved the process for factory and client, lowered down the time and cost of gas filling process.
2008 Best Associate Award
GRAD PROJECTS
•Integrated Analog Circuit Design
1. Designed and simulated a High gain, Stabilized, maximum output swing (pre/post layout) Two-Stage Opamp with miller compensate based on Cadence Virtuoso.
2. Designed a 8 bits high speed, high accuracy, low power consumption Pipeline A/D Converter with 0.65um technology based on Cadence Virtuoso.
3. Developed 0.25 um front end channel circuit with low-noise, low power consumption design (charge amplifier and shaper) based on Matlab and verified Within Cadence Virtuoso.
•Advanced VLSI System Design
1.Gate level design (include layout) within Cadence Virtuoso: INVERTER, XOR, NAND, Flip-Flop. Design, optimized and verified A High-Speed 4 Bit Adder, targeted at high frequency and low power consumption.
2.Develop a dual issue RISC-Style Microprocessor based on Sony Cell SPU prototype, supported with Mips instruction set architecture, Implemented with Verilog code.
3.Design and verified Stream Cipher Encoder/Decoder RTL code within modelsim, coding with System Verilog, Developed Code Generator implemented with C++.
•Embedded System Hardware and Software Co-Design ...
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