Objective:
Design engineer seeking employment in order to make a positive contribution to my employer’s organization through use of my technical abilities and experience.
Professional Experience:
Digital Hardware Design Engineer
Flop Logic, Incorporated
Allen, Texas (June 2002 – Aug 2015)
A list of the projects I have personally designed and been responsible for, follows:
Responsible for the design of a high-speed backplane for a 10 slot telecommunications system shelf. The backplane connectivity design was implemented in the customer specified format using an Excel spreadsheet with various scripts used to create the properly formatted netlist for importation into Cadence Allegro as well as creating other documentation. The scripts were customer supplied, but were not functional and had to be debugged, updated and made functional. The design came directly from a reference design using Molex Impel connectors with architectural changes made to accommodate the specific customer requirements. Following the Molex layout pattern and constraints from the reference design, the design was completed through layout in Allegro. Characterization and functional testing will follow.
Responsible for the complete design of block of the system architecture utilizing a Spartan 6 FPGA whose functionality was to take 2 input serial data streams from 2 ADC converters, deserialize the input streams, run an FFT on each parallelized stream, then compute the magnitude for each stream. The data from each sub-segment (real-time data, FFT output data and magnitude output data) was placed into DPRAM for the system level microcontroller (uC) to access through the FPGA-uC interface. The design, bring-up testing and debug was completed and the entire system went through system integration testing with no reported anomalies after project hand-off to the customer.
Responsible for the system and circuit design of a video display interface board for the Texas Instruments (TI) OMAP5430 PANDA5 board. The board design took the GPMC bus from the PANDA board and converted the bus to a dual channel LVDS display interface through the use of a TI SN65DSI85 dual channel display controller. The design also featured an HDMI output through the use of a TI TFP410 DVI Transmitter coming from the OMAP parallel display interface. The schematic design was captured in OrCAD. The layout rules for the design were specified and layout was checked and amended as necessary. After design, bring-up testing and debug was completed, the boards are through to production status.
Responsible for hardware design support for customer embedded processor designs using the TI line of OMAP4, OMAP5 and DaVinci based system-on-chip processors. The requirements for this responsibility included hardware systems architecture, schematic capture, circuit board layout, design prototyping, initial laboratory bring-up & debug, production prototyping and regulatory compliance testing. The elements of the design checks included the OMAP logic connectivity, signal integrity (SI) of data interfaces, power systems design with power integrity (PI) analysis, DDR functional and SI simulation, printed circuit board layout analysis and thermal analysis. The primary interfaces in these customer systems included USB, HDMI, DDR2, DDR3, LPDDR2, PCIe, SATA, SGMII, PoE, I2C, SPI and MIPI camera and video. The design tools used included Cadence, Mentor and Altium design flows. The simulation tools used for SI and PI included Mentor Hyperlynx (primarily) and Cadence Allegro PCB SI (new name for Specctraquest).
Responsible for design of a 450 W, 28 V Power system for a military ground based radio application. The supply had to comply with Mil-Std-1275 for 28 VDC systems. The power system had to comply with SDIP 27 TEMPEST requirements, Mil-Std-461 for emissions and Mil-Std-464 for electro-static discharge and near strike lightning protection. The system consisted of 2 vendor modules, the specifications for which I outlined and wrote, as well as a pair of circuit boards of my design that tied the power system together. The first module was an input filter and protection module. The second module was an isolated 28 VDC power converter module. The circuit boards had to detect and react to over current conditions, under and over voltage conditions and over temperature faults. The output power section of the circuit board provided conversion & filtering for the various output voltage rails required by the system. All portions of the circuit board design were simulated in LTSpice. Schematics were captured in Altium. PI of the boards was checked using Hyperlynx.
Responsible for the system and circuit design of a development and demonstration system for customer’s line of hi-reliability space qualified devices. The system’s functionality was to produce an FFT of a tone sent through the devices of the development board and display the resultant FFT. The waveform comprising the tone was delivered across a USB connection from the host PC and stored in flash memory. The board controller was an FPGA. On command, the waveform was read out from the flash and sent through a signal processing chain that included a SRAM, DAC, ADC and egress and ingress SERDES with a transition through the FPGA after each step. The data finally terminated back into the FPGA which then handed off the data to the customer’s DSP which was set up to process the FFT and display the results. The RTL for the FPGA was coded in VHDL; the FPGA design was fully modeled in Modelsim and used a Cyclone 3 from Altera. Schematics were captured in OrCAD. I defined and oversaw creation of a Windows based GUI used to control the demonstration system. The customer developed the code base for the DSP. I defined the protocol for communication between the control FPGA and the host PC over USB which included a checksum covering the waveform data using IEEE CRC-32.
Responsible for creating testbenches for design validation effort for a customer’s ASIC to FPGA redesign effort. The customer’s ASIC was going end-of-life and had to be replaced. The testbench was written in Verilog to match the original code used in the ASIC design. By customer specification, the objective for the testbench was to check the external interfaces of the new FPGA solution to ensure there were minimal problems between the FPGA and the new PCB. Three problems were found using the testbench that led to no errors in the PCB board when it was released. Testbenches were simulated and run in Modelsim.
Responsible for the design of control system utilizing an FPGA whose functionality was to drive a high voltage output on the circuit board used to drive a high pressure version of an ink-jet nozzle. The high voltage output was controlled by a DAC driven from the FPGA. The waveform used to drive the circuit came from a PC across an SMBus connection and was temporarily stored before being sent into an attached SRAM. On command, the waveform was then read out from the SRAM and output to a DAC which drove the high voltage circuit. A precisely timed, adjustable strobe output was also required and implemented that drove an output pulse during the output of the waveform which was used for driving a camera and flash for use in testing the jet nozzle output. The...
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