Graduate in Computer Engineering with focus on Digital Design, Signal Processing and Embedded Systems. Experience in ASIC/RTL design and verification using VHDL and Verilog. Over 3 years of experience in implementing DSP and multirate DSP techniques on C/C++, FPGA and MATLAB. Experience in developing software and hardware for real-time embedded systems.
Master of Science in Computer Engineering
Western Michigan University, Kalamazoo, MI.
2012 - 2015
Bachelor of Engineering in Electronics and Communication
Visveswaraya Technological University, Bangalore, India.
2008 - 2012
#Programming Languages: C, C++, VHDL, Verilog, MATLAB, Shell Scripting, TCL.
#Protocols: SPI, I2C, CAN, PWM, RS-232, RS-485.
#Software tools: MATLAB/Simulink, Xilinx-ISE/Vivado, GNU-Radio, IDEs-Compilers/Debuggers, Wireshark.
#Simulators: Modelsim-SE, Xilinx-Isim.
#Hardware tools: ChipscopePro, Logic Analyzer, Oscilloscope, soldering.
#Soft skills: Effective communication skills, fast learner and team player.
Software Defined Radio Front-End Implementation Using Xilinx FPGA (Master’s Thesis),
Advisor: Dr. Bradley j. Bazuin. 1/2014 - 4/2015
•RTL design and verification for integer precision mixer using CORDIC algorithm, high rate Cascaded Integrated-Comb filter-decimation, lower rate half-band filter decimation and spectral shaping low pass filter was done in VHDL for Spartan 6 FPGA.
•Developed a FPGA based digital pattern generator and comparator to provide test data and analyse results in real-time for the SDR Front-End.
•Finite precision integer arithmetic simulations were done on MATLAB and verified with the hardware design implemented.
Educational Technology Services
8/2014 – 4/2015
Worked as a graduate tech assistant for Educational Technology Services at Western Michigan University.
•Part-time job was to provide customer support regarding issues related to computer hardware and software.
•Deployed OS using MDT and maintained local and network printers on windows and Linux machines.
Embedded soft-core processor based pattern generator and comparator.
•Designed RTL interface for external CRAM and verified for the timing violations and interfaced to wishbone bus network.
•Developed 32 bit write and 16 bit read FIFO interfaces to provide the data and queue the results from the external interface.
•Firmware for comparator was developed in C. Used Data2MEM (.BMM) to change the firmware images in the FPGA bitstream.
•Designed VHDL based test-bench to validate the functionality of the design.
Inertial Navigation system implementation on FPGA using embedded soft-core processor.
•Designed 32 bit wishbone bus RTL interface in VHDL on Spartan 6 FPGA for ZPU embedded soft-core processor.
•Implemented programmable SPI modules in VHDL for interfacing gyroscope and accelerometer sensors.
•Firmware was developed using C and GCC tool chain on Cygwin a Linux environment on windows.
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