SUMMARY
Engineering professional with extensive experience in the field of semiconductor verification and quality. Background in manufacturing release and physical layout verification. Demonstrated ability to lead mission-focused teams and projects. Excellent problem-solving, analytical and communication skills. Experience with both domestic and international client support roles. Skilled at presenting to large and small groups. Experienced technical writer.
TECHNICAL SKILLS
Applications: Calibre, Assura, Word, ClearQuest, Excel, PowerPoint, OpenOffice, Lotus Notes
OS: Windows XP/7/8, Linux, Unix
Languages: Light UNIX, shell and Python scripting.
Concepts: LEAN Manufacturing, Failure Mode Effects Analysis (FMEA)
Other: Technical Writing, Program Management, Data Verification, Client support, PC Assembly
TECHNICAL EXPERIENCE
Cyient, Limited, Williston, VT
Foundry Release and Layout Verification Engineer, September 2013 – Present
Position equivalent to that described below under Foundry Release and Layout Verification Engineer.
ipCapital Group, Williston, VT
Technical Writer / Analyst (Independent Contractor), January 2014 – December 2014
Technical writer / analyst for patent disclosures utilizing ipCG methodology. Development includes creation of figures/artwork as well as specification tables and research / embodiment documents for use by the patent attorney team. Perform extensive technical research and documentation to support invention development.
International Business Machines Corporation (IBM), Essex Junction, VT, 1996 – 2013
Foundry Release and Layout Verification Engineer, 2004 – July 2013
Assured quality verification of semiconductor physical design data from active multinational client base utilizing Calibre, Assura and Hercules software ● Engaged in continual analysis and review of project data flow for quality and cycle time improvement ● Performed DRC (design rule checking), pattern density analysis, logistics verification, ground rule waiver implementation and data preparation services ● Supported technician team in all aspects of product release, verification, training and analysis ● Led effort to reduce engineering cycle time by 20% - 50% for a key customer, resulting in substantial improvement in customer satisfaction ● Interviewed and mentored new hires and co-ops ● Facilitated the introduction of CMOS image sensor programs ● Maintained various departmental metrics related to turn around time and serviceability ● Performed light coding in Python, Shell and Unix scripts ● Examined logistical flows to improve turnaround time and eliminate unnecessary processes ● Served as lead engineer on release team for our multi-project wafer (MPW) vendor, responsible for all design submissions, process flows and process improvement ● Utilized Clearquest for creating and tracking improvement recommendations and updates to design kits ● Performed regular and extensive regression testing of features decks resulting in overall kit quality improvement and reduced build errors ● Authored technical design manuals detailing pattern density requirements for all supported foundry technologies, resulting in greater customer
clarity ● Trained in LEAN manufacturing and participated in several LEAN & FMEA sessions to reduce internal quality exposures ● Coordinated and drove weekly release engineering meetings ● ITAR certified ● Provided departmental level hardware and software support, including software debug and install, PC desktop and laptop roll-out.
Hardware Expediter, 2002 – 2010 (as needed)
Performed physical expediting for IBM Systems & Technology Group on an as-needed basis ● Transported time-sensitive hardware to a variety of vendors and clients in Southeast Asia and Eastern Europe ● Ensured proper documentation of hardware for delivery to customs brokers worldwide ● Demonstrated adaptability to diverse cultures ability to navigate international shipping and customs requirements.
Foundry Product Engineer, 1998 – 2004
Managed all technical aspects of client design release from verification and mask creation to wafer build and final deliverable ● Collaborated with high-end clients to develop and introduce 130 nm technologies ● Held regular status meetings both locally and remotely with internal and external clients ● Ported 200 mm designs into new 300 mm facility ● Analyzed and reported wafer yield data ● Oversaw the accurate and efficient introduction of new products into the manufacturing line ● Negotiated design rule waivers, tracked wafer lots through manufacturing line and investigated customer design data issues ● Interfaced regularly with kerf (scribe) developers and technologists for new technology introductions ● Served as product engineering point of contact for all data preparation issues ● Served as lead engineer for introducing pattern density requirements to release teams ● Developed Lotus Notes databases for tracking product status ● Assisted in...
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